| dc.creator | Pérez, Diego | |
| dc.creator | Ropars, Thomas | |
| dc.creator | Meneses, Esteban | |
| dc.date | 2019-08-16 | |
| dc.date.accessioned | 2021-06-11T01:32:48Z | |
| dc.date.available | 2021-06-11T01:32:48Z | |
| dc.identifier | https://revistas.tec.ac.cr/index.php/memorias/article/view/4514 | |
| dc.identifier | 10.18845/mct.v0i0.4514 | |
| dc.identifier.uri | http://hdl.handle.net/2238/13107 | |
| dc.description | Since current multi-core processors are more com- plex systems on a chip than previous generations, some transient errors may happen, go undetected by the hardware and can potentially corrupt the result of an expensive calculation. Because of that, techniques such as Instruction Level Redundancy or checkpointing are utilized to detect and correct these soft errors; however these mechanisms are highly expensive, adding a lot of resource overhead. Hardware Transactional Memory (HTM) exposes a very convenient and efficient way to revert the state of a core’s cache, which can be utilized as a recovery technique. An experimental prototype has been created that uses such feature to recover the previous state of the calculation when a soft error has been found. The combination of HTM, Hyper-Threading and Memory Protection Extensions may further improve the performance, applicability and confidence of our technique. | es-ES |
| dc.format | application/pdf | |
| dc.language | spa | |
| dc.publisher | Instituto Tecnológico de Costa Rica | es-ES |
| dc.relation | https://revistas.tec.ac.cr/index.php/memorias/article/view/4514/4086 | |
| dc.source | Memorias de congresos TEC; 2017: III Jornadas Costarricenses de Investigación en Computación e Informática | es-ES |
| dc.source | 9978-9930 | |
| dc.source | 10.18845/mct.2017.0 | |
| dc.title | Leveraging Modern Multi-core Processor Features to Efficiently Deal with Silent Errors | es-ES |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
| dc.type | Artículo revisado por pares | es-ES |
