Caracterización y Comparación de las Arquitecturas de Unidades Centrales de Procesamiento Generadas en Rocketchip

Abstract

This paper reports the measurement power of the Rocket architectures generated by the Rocketchip tool. The characterization was carried out by the use of VCS and Verilator simulators and by the practical implementation of a Zedboard, measuring the clock cycles and instructions counted in the execution of programs written in C language. To measure the e ciency of the instructions added by the extensions, the CPI was calculated in the di erent Benchmarks to obtain the average cycles that take each instruction. The programs used were a set of RISC-V benchmarks (found in the Rocketchip tool repertoire), a suit applied to the MSP430 processor (found in the bibliography) and the Dhrystone program. The RISC-V suit was used to measure the performance of the additions, operations in memory and execution of multiplication by software. The suit of the MSP430 is used to compare the measure the performance of mathematical operations, lters, state machines and memory with this processor. Practical results were also compared with simulator's results. The Dhrystone program served to compare the performance of Rocket processors implemented with others found in the literature with similar characteristics. By a power report made on Vivado, it was estimated the dynamic power consumption.