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Development of a multi-core and multi-accelerator platform for approximate computing
dc.contributor.advisor | M.Sc. Jorge Castro Godínez | es |
dc.contributor.author | Osorio-Marín, Pablo Felipe | |
dc.date.accessioned | 2019-03-08T14:12:40Z | |
dc.date.available | 2019-03-08T14:12:40Z | |
dc.date.issued | 2017 | |
dc.identifier.uri | https://hdl.handle.net/2238/10374 | |
dc.description | Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2017. | es |
dc.description.abstract | Changing environment in the current technologies have introduce a gap between the ever growing needs of users and the state of present designs. As high data and hard computation applications moved forward in the near future, the current trend reaches for a greater performance. Approximate computing enters this scheme to boost a system overall attributes, while working with intrinsic and error tolerable characteristics both in software and hardware. This work proposes a multicore and multi-accelerator platform design that uses both exact and approximate versions, also providing interaction with a software counterpart to ensure usage of both layouts. A set of five di↵erent approximate accelerator versions and one exact, are present for three di↵erent image processing filters, Laplace, Sobel and Gauss, along with their respective characterization in terms of Power, Area and Delay time. This will show better results for design versions 2 and 3. Later it will be seen three di↵erent interfaces designs for accelerators along with a softcore processor, Altera’s NIOS II. Results gathered demonstrate a definitively improvement while using approximate accelerators in comparison with software and exact accelerator implementations. Memory accessing and filter operations times, for two di↵erent matrices sizes, present a gain of 500, 2000 and 1500 cycles measure for Laplace, Gauss and Sobel filters respectively, while contrasting software times, and a range of 28-84, 20-40 and 68-100 ticks decrease against the use of an exact accelerator. | es |
dc.language.iso | eng | es |
dc.publisher | Instituto Tecnológico de Costa Rica | es |
dc.subject | Aceleradores | es |
dc.subject | Interfaces | es |
dc.subject | Aproximaciones | es |
dc.subject | Plataforma | es |
dc.subject | Transformada de Laplace | es |
dc.subject | Paralelismo | es |
dc.subject | Acceso | es |
dc.subject | Memoria | es |
dc.subject | Procesadores | es |
dc.subject | Potencia | es |
dc.subject | Tiempo | es |
dc.subject | Rendimiento | es |
dc.subject | Research Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electronics | es |
dc.title | Development of a multi-core and multi-accelerator platform for approximate computing | es |
dc.type | tesis de licenciatura | es |