Diseño y Evaluación de Arquitecturas de Enrutador Basado en Tablas de Enrutamiento Estáticas Orientadas al uso en \Network on Chip

Abstract

This work presents an implementation of a parameterized router architecture based on static tables for its use on Network on Chip; For this, a parallel bus of parallel data input with central arbiter was designed, this was later described on System Verilog language, this bus was synthesized logically and physically to check and compare the results of power consumption, area usage and data latency, against other two buses of the project library. Once the functional test were done on the bus, it is used along with decoders, and the FIFOs made of Flip Flops present in the project library to develop a data router architecture. Finally an interconnection generator of type bidimensional net is described in System Verilog language, this architecture keeps exibility in parameters of: width and height of the net, data word width, destiny devise address bits and FIFOs depth.