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Desarrollo de un módulo de decodi cación de la para una memoria SRAM de 2 kb, en un proceso CMOS de 180 nm
(Instituto Tecnológico de Costa Rica, 2018)
At the Instituto Tecnol ogico de Costa Rica, at the Escuela de Ingenier a Electr onica,
the DCILab (Laboratorio de Dise~no de Circuitos Integrados), is currently developing an
ISA RISC-V 32 E microarchitecture, oriented ...
Development of a multi-core and multi-accelerator platform for approximate computing
(Instituto Tecnológico de Costa Rica, 2017)
Changing environment in the current technologies have introduce a gap between the
ever growing needs of users and the state of present designs. As high data and hard
computation applications moved forward in the near ...
Diseño de circuitos de columna para memoria SRAM para su integración en un microprocesador con arquitectura RISCV
(Instituto Tecnológico de Costa Rica, 2018)
En este documento se presenta el diseño de los circuitos periféricos de una memoria
SRAM de 64 palabras con 32 bits, en específico el manejador de escritura y el amplificador
de sensado. La tecnología utilizada es CMOS ...
Verificación funcional de un controlador de memoria para un dispositivo médico implantable.
(Instituto Tecnológico de Costa Rica, 2018)
When a design is made for a product that needs to have a stable and continuous operation
and also that is not expected to fail, the fucntional operation of the devices must be checked
before delivering them to the end ...