Sequential code parallelization for multi-core embedded systems: A survey of models, algorithms and tools

Abstract

In recent years the industry experienced a shift in the design and manufacture of processors. Multiple-core processors in one single chip started replacing the common used single-core processors. This design trend reached the develop of System-on-Chip, widely used in embedded systems, and turned them into powerful Multiprocessor System-onChip. These multi-core systems have presented not only an improvement in performance but also in energy efficiency. Millions of lines of code have been developed over the years, most of them using sequential programming languages such as C. Possible performance gains of legacy sequential code executed in multi-core systems is limited by the amount of parallelism that can be extracted and exploit from that code. For this reason, several tools have been developed to extract parallelism from sequential program and produce a parallel version of the original code. Nevertheless, most of these tools have been designed for high-performance computing systems rather than for embedded systems where multiple constraints must be considered, and a reduction in the execution time is not the only desirable objective. Due there is no definitive solution for parallelizing code, especially for multi-core embedded systems, this work aims to present a survey on some different aspects involved in parallelizing code such as models of code representation, code analysis, parallelism extraction algorithms, parallel programming. Also existing parallelizing tools are presented and compared. This work ends with a recommended list of important key aspects that should be consider when designing and developing a parallelizing compiler, automatic or semiautomatic, for multi-core embedded systems; and when using existing tools to use them.