Diseño de una implementación eficiente en el área de latches pulsados para la técnica Boundary Scan Informe
Abstract
This document establishes a comparison between two di erent topologies for the IEE
1149.1 standard implementation. It is expected to give all the theoretical tools required
to understand the design as well as to establish a comparison of each of the topological
implementations in order to conclude which implementation is more e cient in terms of
area consumption, energy consumption and speed.
Description
Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2018.