Desarrollo de un Convertidos de Tiempo A Digital sobre una Targeta de Desarrollo con FPGA Virtex-5

Abstract

This document synthetize the development of a Time-To-Digital Converter using a development board with a Virtex-5 FPGA. It describes the problem being solve, the institutions related, and the proposed solution. Is also explained how by an engineer study methodology the solution is made. Some of the designs implemented in the FPGA are the RS232 protocol, a signal generator using a PLL, RAM memories, etc. Different alternatives are suggested along the document for each functional block, as well all selections are substantiated. The selected converter corresponds to a linear TDC, and uses a delay line from the DSP slices. There are 48 DSP slices configured, not just by internal registers, but their location within the fpga. A deep study about TDCs and FPGAs functional blocks is made before the selection. The obtained results are exposed in this document; and based on this the conclusions are made.