Optimización de protocolos de comunicación SDR ejecutados en FPGA

Abstract

This project shows a methodology for the optimization digital communication systems implemented on software radios SDR reducing the CPU and memory usage. The project was developed using the kit Zedboard which is based on Xilinx Zynq 7000 series SoC. This SoC is known as hybrid because it counts with a processing systems, PS, based on a ARM processor and a programmable logic based on a FPGA. The PS executes GNU Radio software under a Linux operating System and for the optimizations the communication blocks are implemented on hardware. To communicate PS and PL the Xillybus interface is used. Using Xilinx software tools two commonly used blocks for digital communication transmission and receptors are implemented: a FIR filter and a FFT. Those blocks replace GNU Radio software blocks that perform the same functionality, allowing to execute the same implementation with two different approaches, one completely on software and one on a hybrid system. Memory and CPU usage of the Zedboard for two blocks with the same functionality are compared, the first case is a block running entirely in software and the second in the hybrid system. For FIR filters with 5, 13 and 25 taps CPU usage was 4.52%, 77.73% y 66.92% respectively, the memory usage measured was 25%; for the hybrid system CPU usage is reduced to the values between 15.27%, 8.68% y 4.87% respectively with a memory usage of 24%. For FFT CPU usage was reduced from 96.00% to 32.255% with reduced memory usage from 29% to 24%.