A methodology for the synthesis to logical netlist of an ASIC
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The advances in technology for manufacturing ASICs allow more features to be added. As result, and depending on the architecture of the ASIC, more functional blocks do exist to support such additional features. This imply requiring more resources to synthesize each functional block into a logical netlist. As the physical design process is completed by a third party, reducing the time to deliver the complete set of synthesis files is critical for the project, so that the engineers can start the quality checks of each netlist earlier than the schedule, and the final product can be both completed and released on schedule. This work describes a methodology that automatically executes the synthesis flow of RTL code to logical netlist on each block that forms an ASIC. It helps keeping a better traceability of changes through the milestones in a project. A simulator of the methodology was implemented in Perl to validate that the complete synthesis runtime of an ASIC is improved, compared against a serial flow approach. Consequently, the time to synthesize the complete set of functional blocks is speedup 8.8 times.
Proyecto de Graduación (Maestría en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2017.
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