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dc.contributor.advisorChacón-Rodríguez, Alfonsoes
dc.contributor.authorSequeira-Rojas, Jorge Esteban
dc.date.accessioned2017-08-08T21:44:54Z
dc.date.available2017-08-08T21:44:54Z
dc.date.issued2016
dc.identifier.urihttp://hdl.handle.net/2238/7302
dc.descriptionProyecto de Graduación (Licenciatura en Ingeniería en Electrónica) Instituto Tecnológico de Costa Rica. Escuela de Ingeniería Electrónica, 2016.es
dc.description.abstractA methodology that measures the DSP performance of a ASP with low-power target applications is presented. Additionally, the timing, area and power synthesis results for an adder, a multiplier and a CORDIC oating point units in Artix 7 FPGA family and 0.13 m technology for single and double precision in various system frequencies, are presented. The pipelined adder achieves a maximum frequency of 350MHz, the multiplier (with a simple Karatsuba signi cand multiplication) reaches 243MHz, and lastly, the standalone CORDIC oating point operator reaches 537MHz.es
dc.language.isospaes
dc.publisherInstituto Tecnológico de Costa Ricaes
dc.subjectFPUes
dc.subjectKaratsubaes
dc.subjectCORDICes
dc.subjectBenchmarkinges
dc.subjectASPes
dc.subjectResearch Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electrical engineeringes
dc.titleDiseño e implementación de una Unidad Aritmética de Coma Flotante (FPU) genérica y fexiblees
dc.typelicentiateThesises


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