Diseño e implementación de una Unidad Aritmética de Coma Flotante (FPU) genérica y fexible

dc.contributor.advisor	Chacón-Rodríguez, Alfonso	es
dc.contributor.author	Sequeira-Rojas, Jorge Esteban
dc.date.accessioned	2017-08-08T21:44:54Z
dc.date.available	2017-08-08T21:44:54Z
dc.date.issued	2016
dc.identifier.uri	https://hdl.handle.net/2238/7302
dc.description	Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica. Escuela de Ingeniería Electrónica, 2016.	es
dc.description.abstract	A methodology that measures the DSP performance of a ASP with low-power target applications is presented. Additionally, the timing, area and power synthesis results for an adder, a multiplier and a CORDIC oating point units in Artix 7 FPGA family and 0.13 m technology for single and double precision in various system frequencies, are presented. The pipelined adder achieves a maximum frequency of 350MHz, the multiplier (with a simple Karatsuba signi cand multiplication) reaches 243MHz, and lastly, the standalone CORDIC oating point operator reaches 537MHz.	es
dc.language.iso	spa	es
dc.publisher	Instituto Tecnológico de Costa Rica	es
dc.subject	FPU	es
dc.subject	Karatsuba	es
dc.subject	CORDIC	es
dc.subject	Benchmarking	es
dc.subject	ASP	es
dc.subject	Research Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electrical engineering	es
dc.title	Diseño e implementación de una Unidad Aritmética de Coma Flotante (FPU) genérica y fexible	es
dc.type	tesis de licenciatura	es