Investigación sobre la posible prevención de fallas falsas de un procesador en las pruebas de verificación de calidad

Abstract

The project “PPV false failures reduction investigation”, was developed at Componentes Intel de Costa Rica S.A. located at La Ribera de Belén, Heredia, Costa Rica. This work lied in an investigation which main goal was to study the false failures of the POST process of a specific processor, during the test realized at the Product Platform Validation in order to propose corrective measures. Well designed mechanical and electrical experiment were conducted with the intention of understand the nature of the false failures; as well as determinate the influence of the equipment’s different physical variables (mechanical, thermal and electrical) over the false failures appearance. Some of the achievements were to determinate that the pressure of the mechanical parts use by the equipment to hold the processor through the test time; and the transfer rate of the data through the serial port that communicate the hardware with the test program, were affecting the test results. Furthermore one of the conclusions was that the randomly appearance of an error generated by a lost of communication between the test program and the hardware provoked this false failures.