Implementación de la etapa de arranque (bootstrap) de un microprocesador basado en RISC-V para el Sistema de Reconocimiento de Patrones Acústicos (SiRPA).

Abstract

In the following work, a unit of program instruction loading (hereinafter bootstrap unit) was carried on the RISC-V based microprocessor of the Acoustic Pattern Recognition System (SiRPA). At the time of the development of this project, the memory map architecture for the SiRPA project microprocessor was being restructured, so the unit to be implemented was made under the concept of using a single port SRAM as a memory bank. The unit has the communication functions, in SPI protocol, with the program source, data bus controller and the instruction program writing in memory. This system was implemented on an FPGA, in order to perform functional tests of communication with the source of the program, a micro SD card. In addition, the unit was implemented at the logic implementation level in the Synopsys tool, in 180 nm technology. Finally, the bootstrap unit is compatible with a large number of SDSC and SDHC microSD cards, which follow the protocol convention according to the SD Card Association.